Programmable logic devices (PLDs) exist as a well-known type of integrated circuit (IC) that may be programmed by a user to perform specified logic functions. There are different types of programmable logic devices, such as programmable logic arrays (PLAs) and complex programmable logic devices (CPLDs). One type of programmable logic device, known as a field programmable gate array (FPGA), is very popular because of a superior combination of capacity, flexibility, time-to-market, and cost.
An FPGA typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. The CLBs, IOBs, and interconnect structure are typically programmed by loading a stream of configuration data (bitstream) into internal configuration memory cells that define how the CLBs, IOBs, and interconnect structure are configured. The configuration bitstream may be read from an external memory, conventionally an external integrated circuit memory EEPROM, EPROM, PROM, and the like, though other types of memory may be used. The collective states of the individual memory cells then determine the function of the FPGA.
Dedicated logic circuits configured to perform specific functions are commonly embedded into PLDs. For example, devices in the VIRTEX®-4 family of FPGAs manufactured by Xilinx, Inc., include dedicated digital signal processor (DSP) blocks. Each DSP block (also referred to as a tile) includes a pair of multiplier-accumulator (MACC) circuits. The MACC circuits provide a dedicated hardware solution for performing various types of filtering and mathematical functions related to DSP. Some particular DSP applications, however, require logic in addition to the MACC circuits for operation. This additional logic must be configured using the fabric of the FPGA (e.g., using CLB resources).
For example, a MACC may be used to implement a finite impulse response (FIR) filter. In an FIR filter, each input data sample is multiplied by a corresponding coefficient and the result (referred to as an inner product) is accumulated with other results. Some FIR filters, known as symmetric FIR filters, require pairs of data samples to be summed before being processed by the MACC. Presently, to implement a symmetric FIR filter, a pre-adder must be configured using the CLB fabric of the FPGA to sum pairs of data samples. Among basic elements, however, adders and subtractors are among the slowest when programmed into the CLB fabric. Adders and subtractors also consume a large amount of CLB resources. Accordingly, there exists a need in the art for enhanced multiplier-accumulator logic in a PLD.